Floorplanning

What is floor planning?

• A floor planning is the process of placing blocks/macros in the chip/core area.
• Floorplan determine the size of the design cell (or die), create the boundary and core area and creates wire tracks for placement of standard cells. It is also a process of positioning blocks or macros on the die.
• Floorplan is one the critical & important step in Physical design. Quality of your Chip / Design implementation depends on how good is the Floorplan.

Inputs and Outputs of Floorplan:

Inputs

• Gate level netlist (.v)
• Logical (.db) and physical library(mW)
• Timing constraint (SDC)
• Technology file (.tf)
• RC co-efficient files (TLU+ files)

Outputs

• Design Database (Floorplan Completed)
• Die/Block area decided.
• I/O placed – Macros placed
• Standard cell placement area decided
• Blockages are defined.
• DEF file.

Types Of Floorplan

• Two type of the design are possible. 
• Chip Level
• Block Level
• Block level design will be rectilinear and chip level will be rectangular in shape.

Rectangular :- To define this only height and width of the die is required.

Rectilinear :- To define the size more coordinates are required.

Another types of the floorplan.

• Channeled floorplans
• Abutted floorplans
• Narrow-channel floorplans

Channeled floorplans

Figure A

• Channeled floorplans contain spacing between blocks for the placement of top-level macro cells, as shown in Figure.

Abutted floorplans

Figure B

• In the abutted floorplan methodology, blocks are touching and the tool does not allocate space for macro cell placement between blocks.
• Designs with abutted floorplans do not require top-level optimization, as all logic is pushed down into the blocks. However, abutted floorplans might require over-the-block routing to meet design requirements.
• This floorplan style also requires more attention to feedthrough management. Routing congestion might also become an issue for abutted floorplan designs. An example of an abutted floorplan is shown in Figure.

Narrow-channel Floorplans

Figure C

• The narrow-channel floorplan methodology provides a balance between the channeled floorplan and abutted floorplan methodologies.
• You can abut certain blocks in the design where top-level cells are not needed.
• In other areas, you can reserve a channel between certain blocks for top-level clock routing or other special purpose cells. An example of a narrow-channel floorplan is shown in Figure.

Floorplan Control Parameter

Aspect Ratio :-

• Aspect ratio is the ratio between vertical routing resources to horizontal routing resources. If the ratio is 1.0 height and width are the same, therefore the core is a square. If the ratio 3.0 the height is three times the width.

Core Utilization :-

• Utilization defines the area occupied by standard cell, macros and blockages. In general 70% to 80% of the utilization is fixed because more number of inverter and buffer will be add during the process of CTS in order to maintain minimum skew.

Macro Placement Guidelines

• Using FLY line.
• Port communication.
• Macro grouping (Logical Hierarchy).
• Spacing between two macros.
• Macros alignment – orientation.
• Blockages.
• Notches avoiding.
• Macros are rotated as required to optimized wire length.
• Typically, macros are placed around EDGE of block, keeping are large main area for STD cells.
• Make a HALO around the macros.

Spacing between two macros

Blockages

Placement Blockages

• In placement blockages there is a three types of blockages
• Hard (STD cell Blockages)
• Soft (Non-Buffer Blockages)
• Partial Blockages
• Hard (STD cell Blockages)
• Block all STD cell and buffer
• Soft (Non-Buffer Blockages)
• Only buffer can be placed and STD cell cannot be placed.
• Partial Blockages
• By default, a placement blockages has a blockages factor of 100%.
• You can set blockages percentage according to requirements.

Routing Blockages

• Routing blockages block routing resource on one or more layers.

Halo (Keep-Out Margin)

• It is region around the boundary of fixed macros in design in which no other macros or std-cell can be placed.
• It allow placement of buffers and inverter in its area if keep-out margin is soft.
• If we move the macro than halo also move.

After Floorplan Checklist

• Hard macro placement done according to guidelines?
• Proper blockages created over and around macros?
• Pins and pad placement done according to given constraints or flyline analysis?

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Disclaimer:-
The content on this blog is contributed/derived from various sources. If you feel that there is any copy right violation please leave a comment and it will be removed. :)

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