Placement



 What is Placement?

  • In this stage all the standard cells are placed in the design.
  • Tool determine the location of each of the standard cell on the die.
  • Placement does not just place the standard cell available in the synthesized netlist. It also optimize the design.
  • Placement will be driven by different criteria like timing driven congestion driven, power optimization.
Goal of placement 
  • Timing, Power, Area optimization.
  • Routable design.
  • No/minimal cell density, pin density.
  • Minimal timing DRCs.
Inputs and Outputs of Placement

Inputs
  • Netlist.
  • Floorplanned design.
  • Logical and physical libraries.
  • Design constraint.
Outputs
  • Physical layout information Cell 
  • placement location
Flow of placement
  • Before the start of placement optimization all wire load model (WLM) are removed.
  • Placement uses RC values from virtual route (VR) to calculate timing.
  • VR is the shortest Manhattan distance between two pins.
  • VR RCs is more accurate than WLM RCs.
Placement is performed in four optimization phases.
  • Pre-placement optimization.
  • In placement optimization.
  • Post Placement Optimization (PPO) before clock tree synthesis (CTS).
  • PPO after CTS.
Pre-Placement optimization
  • Pre-placement Optimization optimizes the netlist before placement, HFNs are collapsed. It can also downsize the cells.

In-placement optimization
  • In-placement optimization re-optimizes the logic based on VR. This can perform cell sizing, cell moving, cell bypassing, net splitting, gate duplication, buffer insertion, area recovery. Optimization performs iteration of setup fixing, incremental timing and congestion driven placement.
Post placement optimization
  • Post placement optimization before CTS performs netlist optimization with ideal clocks. It can fix setup, hold, max trans/cap violations. It can do placement optimization based on global routing. It re does HFN synthesis.

Post placement optimization
  • Post placement optimization after CTS optimizes timing with propagated clock. It tries to preserve clock skew.
Placement Stages
Placement perform in three phase.
  • Global Placement
  • Legalization
  • Detailed Placement
Global Placement

  • Global placement aims at generating a rough placement solution that my violate some placement constraint while maintaining a global view of whole netlist.
  • Objective :- To minimize the interconnect wire length.
Legalization
  • Legalization make the rough solution from global placement legal ( i.e. no placement constraint violation ) by moving modules around locally.
Detailed Placement

  • Detailed placement further improve the legalized placement solution in an iterative manner by rearranging a small group of modules in a local region while keeping all other modules fixed.
Timing Driven Placement
  • Timing-driven placement tries to place cells along timing-critical path close together to reduce net RCs and meet setup timing.
Congestion Driven Placement
  • Congestion-driven placement tries to spread the cells along to reduce the track usage.
Different task in placement
  • HFNS (High Fan-out Net Synthesis )
  • Scan chain re-ordering
  • Special cell adding
HFNS (High Fan-Out Net Synthesis)
  • High fan-out net synthesis (HFNS) is the process of buffering the high fanout nets to balance the load.
Why HFNS?
  • To balance the load HFNS is performed too many load affects delay numbers and transition times. Because load is directly proportional to the delay. By buffering the HFN the load can be balanced this is called as high fan-out net Synthesis.
Where HFNS?
  • Generally at placement step HFNS performed. And also be perform during synthesis in design compiler.
Scan chain Re-ordering.
  • IC-compiler can perform placement aware reordering of scan cells.
  • The scan chain information (SCANDEF) from synthesis can be transferred to IC compiler in two way:
    • By loading the netlist in ddc format (embedded SCANDEF).
    • By loading a SCANDEF file (generated after scan insertion) .
Scan Chain Re-Ordering.
  • Scan chain not re-ordered. It will create congestion & degrade overall QoR.
Same flop placement with scan-chain reordered has better congestion & wire / net length are reduce.
  • Re-ordered scan chain. Reduced congestion

Optimization Technique

  • Netlist restructuring only changes existing gates, does not change functionality.

Optimization Technique
  • Cloning
    • Duplicating gates
  • Gate Sizing
  • Buffering
  • Redesigning fanout trees can change delays on specific paths
  • Swapping commutative pins can change the final delay.
Cloning
  • Duplicating Gates
Gate Sizing
Buffering
Redesigning fanout trees can change delays on specific paths

Swapping commutative pins can change the final delay


Note:- To study in detail about above optimizing concept refer VLSI Physical Design: From Graph Partitioning to Timing Closure book.

Checks After Placement
  • Check legalization.
  • Check PG connections of all the cells.
  • Check congestion, place density & pin density maps, All these should be under control.
  • Timing QoR, There should not be any high WNS violations.
  • Minimal max tran & max cap violations.
  • Check whether all don’t touch cells & nets are preserved.
  • What is the total utilization of the design after placement?
  • Setup Timing violations Solved ?
  • Congestion is Acceptable ?
  • What is the maximum Overflow ?
=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=

Disclaimer:-
The content on this blog is contributed/derived from various sources. If you feel that there is any copy right violation please leave a comment and it will be removed. :)

=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=

Comments

Post a Comment