What is sign off?
- Sign off is a process of logical and physical verification of our chip.
Three types of checks done in sign off stage
- Logical Checks
- Physical Checks
- Power Checks
Sign-off Checks
Logical Checks
- LEC ( Logical Equivalence Checks)
- Post Layout STA
Physical Checks
- LVS (Layout vs Schematics)
- DRC (Design Rule Checks)
- ERC (Electrical Rule Check)
- Antenna Check
Power Checks
- Dynamic IR
- EM (Electromigration)
Logical Checks
- LEC (Logical Equivalence Checks)
- Ensure the functional check between RTL and Netlist.
- LEC can be perform between any two representations of a design: RTL vs Netlist OR Reference Netlist vs Golden netlist.
- Inputs: Library files, golden Netlist, reference netlist
Post Layout STA
- All timing checks are performed again using the actual parasitic extracted after the routing of design.
- INPUTS: library files, constraints file, routed netlist, SPEF (SBEF/SDF)
- Tools: Prime Time from synopsys, tempes from cadence.
- Tool to generate RC extraction: starRC, QRC
- Input needed for starRC: .tf, .nxtgrdn(generated from .itf file using grdgenxo tool), GDS-II or DEF/LEF
- Timing checks perform: setup checks , hold checks, DRC checks.
Physical Checks
LVS (Layout vs Schematics)
- Inputs: .v netlist of the design, GSD-layout database of the design, LVS rule deck (.v and GDS should be of the same stage).
- LVS rule deck file contains the layer definition to identify the layers used in layout file and to match it with the location of layer in GDS. It also contains device structure definitions.
LVS check involve three steps:
- Extraction:
- The tool takes GDSII file containing all the layers and uses polygon based approach to determine the components like transistors, diodes, capacitors and resistors and also connectivity information between devices presented in the layout by their layers of construction. All the device layers, terminals of the devices, size of devices, nets, vias and the locations of pins are defined and given an unique identification.
- Reduction:
- All the defined information is extracted in the form of netlist.
- Comparison:
- The extracted layout netlist is then compared to the netlist of the same stage using the LVS rule deck. In this stage the number of instances, nets and ports are compared. All the mismatches such as shorts and opens, pin mismatch etc.. are reported. The tools also checks topology and size mismatch.
LVS check includes following comparisons:
- Number of devices in schematic and its layout.
- Type of devices in schematic and its layout.
- Number of nets in schematic and its layout.
Typical errors which can occur during LVS checks are:
- Shorts: Shorts are formed, if two or more wires which should not be connected together are connected.
- Opens: Opens are formed, if the wires or components which should be connected together are left floating or partially connected.
- Component mismatch: Component mismatch can happen, if components of different types are used (e.g, LVT cells instead of HVT cells).
- Missing components: Component missing can happen, if an expected component is left out from the layout.
- Parameter mismatch: All components has it’s own properties, LVS tool is configured to compare these properties with some tolerance. If this tolerance is not met, then it will give parameter mismatch.
DRC (Design Rule Checks)
- Design rule checks are nothing but physical checks of metal width, pitch and spacing requirement for the different layers with respect to different manufacturing process.
- If we give physical connection to the components without considering the DRC rules, then it will lead to failure of functionality of chip, so all DRC violations has to be cleaned up.
- After the completion of physical connection, we check each and every polygon in the design, based on the design rules and reports all the violations. This whole process is called Design Rule Check.
Typical DRC rules are:
- Interior
- Exterior
- Enclosure
- Extension
Interior
Exterior
Enclosure
Extension
ERC (Electrical Rule Checks)
- ERC involves checking a design for all electrical connection.
- Checks such as:
- Well and subtract area for proper contact and spacing.
- Unconnected input or shorted output.
- Gates should not connect directly to supply (Must be connect through TIE high/low cells only).
- Floating gate error:
- If any gate is unconnected, this could lead to leakage issues.
- VDD/VSS errors:
- The well geometries need to be connected to power/Ground and if the PG connection is not complete or if the pins are not defined, the whole layout can report errors like “NWELL not connected to VDD.
Antenna Check
- The antenna effect is caused by the charges collected on the floating interconnects, which are connected to only a gate oxide. During the metallization, long floating interconnects act as temporary capacitors and store charges gained from the energy provided by fabrication steps such as plasma etching and CMP. If the collected charges exceed a threshold, the Fowler-Nordheim (F-N) tunneling current will discharge through the thin oxide and cause gate damage. On the other hand, if the collected charges can be released before exceeding the threshold through a low impedance path, such as diffusion, the gate damage can be avoided.
- For example, considering the routing in Figure A, the interconnects are manufactured in the order of poly, metal 1, and metal 2. After manufacturing metal 1 (see Figure B), the collected charges on the right metal 1 pattern may cause damage to the connected gate oxide. The discharging path is constructed after manufacturing metal 2 (see Figure C), and thus the charges can be released through the connected diffusion on the left side.
Solution for antenna violation
- There are three kinds of solutions to reduce the antenna effect.
- Jumper insertion: Break only signal wires with antenna violation and route to the highest level by jumper insertion. This reduces the charge amount for violated nets during manufacturing.
- Embedded protection diode: Add protection diodes on every input port for every standard cell. Because these diodes are embedded and fixed, they consume unnecessary area when there is no violation at the connecting wire.
- Diode inserting after placement and routing: Fix those wires with antenna violations that have enough room for “under-the-wire” diode insertion. During wafer manufacturing, all the inserted diodes are floating (or ground). One diode can be used to protect all input ports that are connected to the same output ports. However, this approach works only if there is enough room for diode insertion.
Power Checks
EM – electro migration
- EM leads to open circuits due to voids in wires or vias and leads to short circuits due to extrusions or “hillocks” on wires. During older technology nodes EM was considered only on power wires and clock wires, But now signal wires also need to be considered due to increased current density in them.
Method to fix EM
- Widen the wire to reduce current density.
- Keep the wire length short.
- Reduce buffer size in clock lines.
- Lower the supply voltage.
IR drop
- IR Drop can be defined as the voltage drop in metal wires constituting power grids before it reaches the vdd pins of the cells.
- IR drop occurs when there are cells with high current requirement or high switching regions.
- IR drop causes voltage drop which in-turn causes the delaying of the cells causing setup and hold violations. Hold violations cannot be fixed once the chip is fabricated.
Two types of IR drop
- Static IR drop analysis
- Dynamic IR drop analysis
Method to reduced IR drop
- Robust power mesh
- De-cap Cell
- Spacing
- Reducing load
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Disclaimer:-
The content on this blog is contributed/derived from various sources. If you feel that there is any copy right violation please leave a comment and it will be removed. :)
=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=
- Sign off is a process of logical and physical verification of our chip.
Three types of checks done in sign off stage
- Logical Checks
- Physical Checks
- Power Checks
Sign-off Checks
Logical Checks
- LEC ( Logical Equivalence Checks)
- Post Layout STA
Physical Checks
- LVS (Layout vs Schematics)
- DRC (Design Rule Checks)
- ERC (Electrical Rule Check)
- Antenna Check
Power Checks
- Dynamic IR
- EM (Electromigration)
Logical Checks
- LEC (Logical Equivalence Checks)
- Ensure the functional check between RTL and Netlist.
- LEC can be perform between any two representations of a design: RTL vs Netlist OR Reference Netlist vs Golden netlist.
- Inputs: Library files, golden Netlist, reference netlist
Post Layout STA
- All timing checks are performed again using the actual parasitic extracted after the routing of design.
- INPUTS: library files, constraints file, routed netlist, SPEF (SBEF/SDF)
- Tools: Prime Time from synopsys, tempes from cadence.
- Tool to generate RC extraction: starRC, QRC
- Input needed for starRC: .tf, .nxtgrdn(generated from .itf file using grdgenxo tool), GDS-II or DEF/LEF
- Timing checks perform: setup checks , hold checks, DRC checks.
Physical Checks
LVS (Layout vs Schematics)
- Inputs: .v netlist of the design, GSD-layout database of the design, LVS rule deck (.v and GDS should be of the same stage).
- LVS rule deck file contains the layer definition to identify the layers used in layout file and to match it with the location of layer in GDS. It also contains device structure definitions.
LVS check involve three steps:
- Extraction:
- The tool takes GDSII file containing all the layers and uses polygon based approach to determine the components like transistors, diodes, capacitors and resistors and also connectivity information between devices presented in the layout by their layers of construction. All the device layers, terminals of the devices, size of devices, nets, vias and the locations of pins are defined and given an unique identification.
- Reduction:
- All the defined information is extracted in the form of netlist.
- Comparison:
- The extracted layout netlist is then compared to the netlist of the same stage using the LVS rule deck. In this stage the number of instances, nets and ports are compared. All the mismatches such as shorts and opens, pin mismatch etc.. are reported. The tools also checks topology and size mismatch.
LVS check includes following comparisons:
- Number of devices in schematic and its layout.
- Type of devices in schematic and its layout.
- Number of nets in schematic and its layout.
Typical errors which can occur during LVS checks are:
- Shorts: Shorts are formed, if two or more wires which should not be connected together are connected.
- Opens: Opens are formed, if the wires or components which should be connected together are left floating or partially connected.
- Component mismatch: Component mismatch can happen, if components of different types are used (e.g, LVT cells instead of HVT cells).
- Missing components: Component missing can happen, if an expected component is left out from the layout.
- Parameter mismatch: All components has it’s own properties, LVS tool is configured to compare these properties with some tolerance. If this tolerance is not met, then it will give parameter mismatch.
DRC (Design Rule Checks)
- Design rule checks are nothing but physical checks of metal width, pitch and spacing requirement for the different layers with respect to different manufacturing process.
- If we give physical connection to the components without considering the DRC rules, then it will lead to failure of functionality of chip, so all DRC violations has to be cleaned up.
- After the completion of physical connection, we check each and every polygon in the design, based on the design rules and reports all the violations. This whole process is called Design Rule Check.
Typical DRC rules are:
- Interior
- Exterior
- Enclosure
- Extension
Interior
Exterior
Enclosure
Extension
ERC (Electrical Rule Checks)
- ERC involves checking a design for all electrical connection.
- Checks such as:
- Well and subtract area for proper contact and spacing.
- Unconnected input or shorted output.
- Gates should not connect directly to supply (Must be connect through TIE high/low cells only).
- Floating gate error:
- If any gate is unconnected, this could lead to leakage issues.
- VDD/VSS errors:
- The well geometries need to be connected to power/Ground and if the PG connection is not complete or if the pins are not defined, the whole layout can report errors like “NWELL not connected to VDD.
Antenna Check
- The antenna effect is caused by the charges collected on the floating interconnects, which are connected to only a gate oxide. During the metallization, long floating interconnects act as temporary capacitors and store charges gained from the energy provided by fabrication steps such as plasma etching and CMP. If the collected charges exceed a threshold, the Fowler-Nordheim (F-N) tunneling current will discharge through the thin oxide and cause gate damage. On the other hand, if the collected charges can be released before exceeding the threshold through a low impedance path, such as diffusion, the gate damage can be avoided.
- For example, considering the routing in Figure A, the interconnects are manufactured in the order of poly, metal 1, and metal 2. After manufacturing metal 1 (see Figure B), the collected charges on the right metal 1 pattern may cause damage to the connected gate oxide. The discharging path is constructed after manufacturing metal 2 (see Figure C), and thus the charges can be released through the connected diffusion on the left side.
Solution for antenna violation
- There are three kinds of solutions to reduce the antenna effect.
- Jumper insertion: Break only signal wires with antenna violation and route to the highest level by jumper insertion. This reduces the charge amount for violated nets during manufacturing.
- Embedded protection diode: Add protection diodes on every input port for every standard cell. Because these diodes are embedded and fixed, they consume unnecessary area when there is no violation at the connecting wire.
- Diode inserting after placement and routing: Fix those wires with antenna violations that have enough room for “under-the-wire” diode insertion. During wafer manufacturing, all the inserted diodes are floating (or ground). One diode can be used to protect all input ports that are connected to the same output ports. However, this approach works only if there is enough room for diode insertion.
Power Checks
EM – electro migration
- EM leads to open circuits due to voids in wires or vias and leads to short circuits due to extrusions or “hillocks” on wires. During older technology nodes EM was considered only on power wires and clock wires, But now signal wires also need to be considered due to increased current density in them.
Method to fix EM
- Widen the wire to reduce current density.
- Keep the wire length short.
- Reduce buffer size in clock lines.
- Lower the supply voltage.
IR drop
- IR Drop can be defined as the voltage drop in metal wires constituting power grids before it reaches the vdd pins of the cells.
- IR drop occurs when there are cells with high current requirement or high switching regions.
- IR drop causes voltage drop which in-turn causes the delaying of the cells causing setup and hold violations. Hold violations cannot be fixed once the chip is fabricated.
Two types of IR drop
- Static IR drop analysis
- Dynamic IR drop analysis
Method to reduced IR drop
- Robust power mesh
- De-cap Cell
- Spacing
- Reducing load
=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=
Disclaimer:-
The content on this blog is contributed/derived from various sources. If you feel that there is any copy right violation please leave a comment and it will be removed. :)
=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=
Disclaimer:-
The content on this blog is contributed/derived from various sources. If you feel that there is any copy right violation please leave a comment and it will be removed. :)
=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=
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