Routing

What is Routing?

• Routing is the process of creating physical connections based on logical connectivity.

Inputs and Outputs Of Routing


Inputs

• Netlist with location of blocks and locations of pins (CTS Completed).
• Timing budget for critical net.
• Technology File
• TLU+ File
• SDC

Outputs

• Geometric layout of all nets (.GDS)
• .spef file
• .sdc file

Checklist Before Routing

• Placement completed
• CTS completed
• Power and ground nets routed
• Estimated congestion - acceptable
• Estimated timing – acceptable (~0 ns slack)
• Estimated max cap/trans – no violations

Routing Constraint

Design rule constraint

• Design rule constraints are often related with the manufacturing details during fabrication. To improve the manufacturing yield, connections of nets have to follow the rules provided by foundries. It also includes RC value of each layer.

Types Of Routing

• Power routing.
• Clock routing.
• Signal routing.
• Critical routing.

Power Routing

• In the power routing VDD and VSS are routed in power routing.

Clock Routing

• After CTS, clock is routed.

Signal Routing

• In the routing stage all the signal pins are routed.

Routing operation stages

• Global Routing
• Track Assignment
• Detailed Routing
• Search and Repair

Global Routing

• first partitions the routing region into tiles/rectangles called global routing cells (gcells) and decides tile-to-tile paths for all nets while attempting to optimize some given objective function (e.g., total wire length and circuit timing), but doesn’t make actual connections or assign nets to specific paths within the routing regions.
• By default, the width of a gcells is same as the height of a standard cell and is aligned with the standard cell rows.
• Every gcell having the a number of horizontal routing resources and vertical routing resources.
• Global routing assigns nets (logical connectivity not metal connectivity) to specific metal layers and global routing cells.

Track Assignment

• Track assignment is a stage wherein the routing tracks are assigned for each global routes. The tasks that are performed during this stage are as follows
• Assigning tracks in horizontal and vertical partitions.
• Rerouting all overlapped wires.
• Track Assignment replaces all global routes with actual metal layers.
• Although all nets are routed (not very carefully), there will be many DRC, SI and timing related violations, especially in regions where the routing connects the pins. These violations are fixed in the succeeding stages.

Detail Routing

• The detailed router uses the routing plan laid by the router during the Global Routing and Track Assignment and lays actually metal to logically connect pins with nets and other pins in the design.
• The violations that were created during the Track Assignment stage are fixed through multiple iterations in this stage.
• The main goal of detailed routing is to complete all the required interconnect without leaving shorts or spacing violations.
• The detailed routing starts with the router dividing the block into specific areas called switch boxes or Sbox, which are generally expressed in terms of gcells.

Search and Repair

• The search-and-repair stage is performed during detailed routing after the first iteration. In search-and-repair, shorts and spacing violations are located and rerouting of affected areas to fix all possible violation is executed.

Types of Detail Routing

• Grid-Based Routing
• Grid-Less Routing

Grid-Based Routing

Grid-Based Routing

• For grid-based routing, a routing grid is superimposed on the routing region, and then the detailed router finds routing paths in the grid.
• The space between adjacent grid lines is called wire pitch, which is defined in the technology file and is larger than or equal to the sum of the minimum width and spacing of wires.
• Switching from layer to layer is allowed only at the intersection of vertical and horizontal grid lines. In this way, the wires with the minimum width following the path in the grid would automatically satisfy the design rules.
• Therefore, grid-based detailed routing is much more efficient and easier for implementation.

Grid-Less Routing

Grid-Less Routing

• A gridless detailed router does not follow the routing grid and thus can use different wire widths and spacing.
• It can handle variable widths and spacing for wires and is, thus, more suitable for interconnect tuning optimization, such as wire sizing.
• However, gridless detailed routing is generally much slower than the grid-based one because of its higher complexity.

Routing Congestion

• Routing congestion occurs when too many routes need to go through an area that does not have enough resources or routing tracks.
• High speed design having more signal integrity constraints such as extra route spacing or wire routes.

Causes of Congestion

Floorplan Congestion

• Between memories & around corner of memories.

High placement density

• Timing is tightly constrained without taking wire impact into account or optimized using excessive buffering or sizing.

Logic induced congestion

• High amount of connectivity contained within a small area. i.e. Large mux/ High pin density in small cell.
• Limited numbers of routing layer for cost reason can also cause global congestion.

Solution For Congestion

Floorplan Congestion

• Creating more space around the macros.
• Placement blockages.
• Macro Orientation change.

High placement density

• Spreading of standard cells.
• Remove buffers and pairs of inverters before placement.
• Decreasing the overall target utilization.

Check List After Routing

• Special cells are inserted.
• Final utilization (total & cell row).
• Final congestion figure.
• Power analysis done?
• Total power consumption in design.
• Timing analysis for setup & hold slack.

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Disclaimer:-

The content on this blog is contributed/derived from various sources. If you feel that there is any copy right violation please leave a comment and it will be removed. :)

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